Single Cycle RISC-V Processor

Overview:

A 32-bit single-cycle RISC-V core written from scratch in Verilog — datapath, control unit, register file, and ALU.

Verification:

The core was validated against more than 40 directed test cases, covering each ALU operation and every branch condition rather than only the happy path.

Writing the tests alongside the RTL meant a broken control signal showed up as a failing case instead of as a mystery further down the line.